Contact Person: B. Srinivasa Raju, Mail your resume to him if you are interested!
Contact #:
A *scheduled hiring event *will be conducted on 23rd November 2009 at
BTP for the Service Engineering and Operations group.
*Req:* 25696
*Location*: Bangalore
We are looking to hire Senior Systems Engineer with 3 to 5 years of
experience
Responsibilities:
- Working on reliability, scalability and performance aspects of
distributed applications
- Working with large scale production deployments of thousands of
servers
- Building tools to manage, monitor and trouble shoot large scale
networks
- Participate in a 12x7 (daylight hours) on-call pager rotation
Requirements:
- Operating systems (Linux or similar forms of Unix)
- Perl or UNIX scripting
- Understanding of DNS, NFS, TCP/IP, Apache etc
- Good understanding of UNIX architecture & internals
- Utilize strong analytical and problem solving skills to
diagnose/resolve system and application issues
- Monitoring tool knowledge such as Nagios, Ganglia etc
- Working on the reliability, scalability and performance aspect of
distributed Application/OS
- MySQL Knowledge
Friday, November 20, 2009
Employee Referral - Symm Software Group
Posted by R BANDARU at 11:16 AM
Contact Person: Prabhu Ganesh
Contact #:
Contact #:
Group - Symmetrix Software group Req Number - 47551BR Position - Software Engineer Exp - 2 to 5 yrs Hiring Mgr - Seetharaman, Loganathakumar This position is for the Enginuity (internally known as microcode) product which is the high available, high performance operating system of Symmetrix. This group offers software solutions to enterprise storage array engineering problems in a challenging ultra speed data IO environment. JOB DESCRIPTION
| |||||||||||||||
Do you know somebody for this role? EMC encourages our employees to refer individuals for employment who can help us continue our success in meeting EMC´s customers' requirements for Enterprise Storage products and services. If you know of a friend, family member or business associate, who is actively looking to make a career move and have expressed an interest in joining EMC please send their resume through Careers India COE : http://indiacoe/Job/ |
Employee Referral - Walkin Scheduled on 21st Nov 09- BE/Btech/MCA
Posted by R BANDARU at 11:15 AM
Contact Person: Raghunandan
Contact #: :# #
We would like to thank you for all the help extended till date in fulfilling our key requirements. Once again we solicit your cooperation and support in fulfilling openings in Java.
We are conducting a weekend drive on 21st Nov 09.
Please ask your referrals to walk-in directly to the venue mentioned below, mentioning the name of the referee on the top of their resume, if they are matching with the criteria.
Contact #: :# #
We would like to thank you for all the help extended till date in fulfilling our key requirements. Once again we solicit your cooperation and support in fulfilling openings in Java.
We are conducting a weekend drive on 21st Nov 09.
Please ask your referrals to walk-in directly to the venue mentioned below, mentioning the name of the referee on the top of their resume, if they are matching with the criteria.
Let us work together in our Endeavour to Scout the Best Talent!!!
1)
Job Position | Software Engineer |
Job Specification | Require minimum 9-18 months experience in Java Development |
Experience | 9-18 months |
Education | BE/BTech/( Preferably Mechanical engineering Background)/MCA |
Location: | Bangalore |
2)
Job Position | Software Engineer |
Job Specification | Require minimum 9-18 months experience in Call center background |
Experience | 9-18 months |
Education | BE/BTech/( Preferably Mechanical engineering Background)/MCA |
Location: | Bangalore |
Walkin Plan:
Date – 21st Nov 09- Saturday
Time- 9.30am- 10.30am
Venue:
ITC Infotech India Limited
ITC Infotech Park
“Food Court”, Banaswadi Main Road
Pulkeshinagar, Cookes Town
Bangalore
Land Mark: Near Bangalore East Railway station
Selection Process: Test and Interview
For any clarification please call on extn 8991
Note: You can directly ask your referrals to come to ITC Infotech on 21st Nov 09 for the selection process and make sure candidates will mention the name of the referee on the top of their resume.
Please refer as many as you can and let us work together to tap talent pool.
Best Regards
Team Recruitment |Talent Management |Direct:# #
Team Recruitment |Talent Management |Direct:# #
2009 passed outs - 24 hour Opportunity !
Posted by R BANDARU at 11:12 AM
Upload your resume here: http://firstnaukri.com/ offcampus/ocDetails.php
Contact #:
Contact #:
To support the organization’s fast-paced growth we need to recruit young talent, who are qualified and possess out of the box thinking abilities. In our quest for looking for these young professionals, we realize the best person to help us in this search could be “YOU.”
If your friends are engineering students from the 2009 batch with specialization in the following streams:
- Information Technology
- Computer Science
- Electronics & Electricals
- Electronics & Communications
- Software engineering
The person can be a BE/ B.Tech /ME /M Tech /MCA /MIT /M.Sc (IT) /MS along with meeting the eligibility criterions specified for his/her college.
Kindly note the few important points while reaching out to someone:
1. Do remember to ask your friends to post their details at http://firstnaukri.com/ offcampus/ocDetails.php by 19 November’2009.
2. They should definitely mention your employee code while applying online.
3. The link will be available for registration & it will removed by COB of Thursday, 19 November’ 2009
4. Resumes received through any other mode of communication will not be considered
5. All the referred profiles might not be called for the written test because of limited business requirements.
Short-listed candidates will be intimated about the date and venue for a test via email. The test will happen in all 3 centers i.e., Gurgaon, Bangalore & Chennai.
In case of any query, please get in touch with V.Radhika @ 3637 in Gurgaon, Shyam @ 6443 in Chennai and Deepa Achuthan @ 7262 in Bangalore.
So go ahead and enjoy the long-lasting reward of contributing to Aricent’s future.
Regards
iRefer Team
Thursday, November 19, 2009
Openings @ AMD
Posted by R BANDARU at 12:07 PM
Contact Person:Vennu SrinivasKumar / K. Aravinth / Manju ( Srinivas Vennu (or) Krishna Murthy ;(or) Manju Mandali)
Contact #: --
ü Physical Design : Place & route, synthesis, Timing, Clock = 3 to 15 yrs of experience for Various Level
ü Verification : 4 to 9 years of experience
ü DFT Implementation : 4+ yrs onwards
A. MTS- ASIC/Layout Design Engineer - GSE Team ()
• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering
• Minimum 7+ years experience in ASIC Design Verification, including 2 years as a verification lead
• At least 2+ years experience in complex ASIC Design Verification, direct experience in SOC or Processor/Graphics/Video is preferred
• Must have excellent knowledge of ASIC Design Flow
• Extensive experience with C & C++ and SystemC
• Experience in developing complex testbench/model in verilog, PLI and/or System verilog
• Excellent debug skills in both functional and gate level simulations are must.
• Experience in random test generation, coverage analysis, failure debug, formal equivalency checking, and Assertions (PSL, SVA)
• Proficiency in common UNIX scripting languages (perl, csh, sh.)
• Knowledge of I/O interfaces like USB2.0, SATA, SD and etc is desired
• Knowledge of 2D/3D Graphics, Video and Display standards is a plus
• Must have good communication skills and the ability and desire to foster a team environment.
B. Senior. Design Engineer- PSE Team ()
· 5 - 7 yrs experience in ASIC/SOC design and verification
Exposure to processor verification is highly preferred
Must have taped-out at least one successful SOC
Appropriate candidate will have the skills of:
• Verilog/High level verification
• SOC verification and random test generation
• Testplanning & test writing especially for processor verification
• Exposure to tools like: VCS/NCSim, Debussy
• Perl and scripting
• Knowledge/exposure to complete SOC tape-out flow
C. MTS- Physical Design- PSE Team ()
· Key Responsibilities
· The position is for a PD staff engineer in the AMD PSE PD group catering to building the next generation fusion SoCs. Fusion programs will cater to the next gen compute requirements bringing in CPU, GPU, MC, Video and other misc functions on an integrated monolithic die. The candidate will technically lead and mentor a team of engineers on Physical Design (place and route ) duties both on block, as well as global top-level activities, which includes: top-level floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis, ECO tasks (timing, functional, noise based ECOs), power delivery etc. Good understanding required of all aspects of physical design taking a design from RTL/ Netlist to GDSII and production. In addition the candidate is expected to have close to expert level of skill in a few core areas.
· The candidates responsibilities will also include flow and methodology development related to the above tasks or new tasks that arise as technology changes. This involves flow design and implementation via coding in various languages. In addition, very strong communication skills and an ability to work in large groups are essential to being successful.
· Excellent debugging skills is a must, candidate must be more than a tool executor, and knows how to diagnose and devise workarounds for problems.
· Requirements
· Minimum 6 years of ASIC physical design experience.
· Leadership and Mentoring skills a must.
· Strong Back ground of ASIC Physical Design : Floor planning , P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.
· Hands on experience and detailed knowledge in Cadence or Synopsys or Magma ASIC Physical Design Tools
· Scripting Language with PERL ,TCL,AWK, shell scripting a very big asset.
· Familiar with Physical Verification is also desirable.
D. DFT/ATPG Flow/Methodology Engineer:
Contact #: --
We are planning to conduct Walk In Interviews at Bangalore office on Sunday 22nd November for the below positions.
Skills in Short
.
Detailed Job Description.
· Key Responsibilities:
• Responsible for participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy for the Graphics chips
• Specifying an overall design verification plan for an full chip SoC
• Specifying or reviewing plans for complex blocks within the ASIC
• Architecting new verification methodologies and evaluating new tools.
• Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes :
o self-checking, reusable, automated verification environment : both at full-chip & block level
o Constrained random generators and reference models
• Being a mentor and technical leader for more junior verification engineers.
• Leading or participating in the ASIC bring-up and debug
· Job Requirements and Skills:• Responsible for participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy for the Graphics chips
• Specifying an overall design verification plan for an full chip SoC
• Specifying or reviewing plans for complex blocks within the ASIC
• Architecting new verification methodologies and evaluating new tools.
• Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes :
o self-checking, reusable, automated verification environment : both at full-chip & block level
o Constrained random generators and reference models
• Being a mentor and technical leader for more junior verification engineers.
• Leading or participating in the ASIC bring-up and debug
• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering
• Minimum 7+ years experience in ASIC Design Verification, including 2 years as a verification lead
• At least 2+ years experience in complex ASIC Design Verification, direct experience in SOC or Processor/Graphics/Video is preferred
• Must have excellent knowledge of ASIC Design Flow
• Extensive experience with C & C++ and SystemC
• Experience in developing complex testbench/model in verilog, PLI and/or System verilog
• Excellent debug skills in both functional and gate level simulations are must.
• Experience in random test generation, coverage analysis, failure debug, formal equivalency checking, and Assertions (PSL, SVA)
• Proficiency in common UNIX scripting languages (perl, csh, sh.)
• Knowledge of I/O interfaces like USB2.0, SATA, SD and etc is desired
• Knowledge of 2D/3D Graphics, Video and Display standards is a plus
• Must have good communication skills and the ability and desire to foster a team environment.
Exposure to processor verification is highly preferred
Must have taped-out at least one successful SOC
Appropriate candidate will have the skills of:
• Verilog/High level verification
• SOC verification and random test generation
• Testplanning & test writing especially for processor verification
• Exposure to tools like: VCS/NCSim, Debussy
• Perl and scripting
• Knowledge/exposure to complete SOC tape-out flow
· Leadership and Mentoring skills a must.
· Strong Back ground of ASIC Physical Design : Floor planning , P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.
· Hands on experience and detailed knowledge in Cadence or Synopsys or Magma ASIC Physical Design Tools
· Scripting Language with PERL ,TCL,AWK, shell scripting a very big asset.
· Familiar with Physical Verification is also desirable.
The job involves developing flows and methodologies for the creation of high quality manufacturing tests for cutting edge designs using structured Design-for-Test (DFT), Automatic Test Pattern Generation (ATPG) and Logic Built-In Self Test (LBIST) techniques/tools. Candidates must have good software engineering skills and strong knowledge of C/C++ and scripting languages such as Perl. Candidates should also be knowledgeable about DFT techniques such as JTAG TAP, MUX-D/LSSD scan, MBIST, on-chip hardware test compression and at-speed test using on-chip PLL. Familiarity with LBIST and architecture/RTL of Design-for-test techniques is an added advantage.
We look forward to your continuous support and more referrals!!!
Please feel free to mail your queries/clarification to the Team – HR.
Team HR.
Wednesday, November 18, 2009
PCB Design Engineer position at Synergy Circuits Pvt Ltd, Bangalore
Posted by R BANDARU at 12:18 PM
Contact Person: Vilma / Sandhya
Contact #: #1 #2
Hi,
This refers to the position we have with our client Synergy Circuits Pvt Ltd
Position : PCB Design Engineer / Sr. PCB Design Engineer
Qualification : BE
Experience : Min 2 + years, Max - upto 7 years
Locations : Bangalore
Job Description :
Candidate must be experienced in PCB Design in PADS software.
Must be able to show multi-tester platform experience.
About the Company :
Synergy Circuits Pvt. Ltd is an US based company dealing with PCB layout solutions.
Synergy Circuits offers end-to-end circuit board layout solutions for quality results and fast turn around. PCB layout is their core business. Utilizing the latest software tools such as Cadence Allegro and Mentor Graphics, they execute to the client’s specific needs and standards. In addition to board layout they also provide documentation and verification design services to achieve complete results.
They are specialized in High-Speed Design, Digital and Analog PCB Design, and high layer designs with complex blind & buried vias.
Synergy Circuits design services include: PCB layout, Schematic capture, Netlist translation, Interactive/auto-routing and Verification
To know more about the company please visit their website www.sysnergycircuits.com
If you find yourself suitable for the above position, please mail the updated copy of your profile to us immediately.
Vilma / Sandhya
Global Search Consultants
Tele:
Contact #: #1 #2
Hi,
This refers to the position we have with our client Synergy Circuits Pvt Ltd
Position : PCB Design Engineer / Sr. PCB Design Engineer
Qualification : BE
Experience : Min 2 + years, Max - upto 7 years
Locations : Bangalore
Job Description :
Candidate must be experienced in PCB Design in PADS software.
Must be able to show multi-tester platform experience.
About the Company :
Synergy Circuits Pvt. Ltd is an US based company dealing with PCB layout solutions.
Synergy Circuits offers end-to-end circuit board layout solutions for quality results and fast turn around. PCB layout is their core business. Utilizing the latest software tools such as Cadence Allegro and Mentor Graphics, they execute to the client’s specific needs and standards. In addition to board layout they also provide documentation and verification design services to achieve complete results.
They are specialized in High-Speed Design, Digital and Analog PCB Design, and high layer designs with complex blind & buried vias.
Synergy Circuits design services include: PCB layout, Schematic capture, Netlist translation, Interactive/auto-routing and Verification
To know more about the company please visit their website www.sysnergycircuits.com
If you find yourself suitable for the above position, please mail the updated copy of your profile to us immediately.
Vilma / Sandhya
Global Search Consultants
Tele:
Jobs in BANK OF INDIA [[GOVT.]]
Posted by R BANDARU at 12:15 PM
Contact Person: -
Contact #: -
Original Notification: !View&Download!
NAME OF THE POST / VACANCIES :
* Under Non-Creamy Layer Category as on 31.03.2009.
Contact #: -
Original Notification: !View&Download!
Probationary Officers (PO) – Recruitment Project 2009-10
Notice dated 20.10.2009
BANK OF INDIA, a leading Public Sector Bank having Head Office in Mumbai, invites applications for recruitment of 1083 post of General Banking Officers in Scale- I, II & III. |
For taking out Challan Click “Print Challan” Button on Page 14 and after making fee payment (for other than SC/ST/PWD & Ex-Servicemen candidates) Click “ Apply online” for the application form provided at the end of Advertisement/Notice – Page- 15.
Challan available from | 09.11.2009 |
Submission of on – line application commencing from | 11.11.2009 |
Last date for submission of on – line application | 30.11.2009 |
Tentative date of Written Examination (Sunday) | 24.01.2010 |
Relevant date of Age/Qualification/Experience reckoned as on | 01.11.2009 |
NAME OF THE POST / VACANCIES :
Post Code No. | Name of the Post | Scale | No. of Vacancies | Out of which PWD | ||||||
SC | ST | OBC* | GEN | TOTAL | OC | VC | HI | |||
001 | General Banking Officers | I | 63 | 30 | 118 | 249 | 460** | 4 | 4 | 4 |
002 | General Banking Officers | II | 65 | 38 | 113 | 170 | 386** | 3 | 3 | 3 |
003 | General Banking Officers | III | 42 | 22 | 70 | 103 | 237** | 2 | 2 | 2 |
Grand Total | 1083** |
** Above vacancy position includes backlog of previous recruitment process.
- As the reservation for PWD candidates is on horizontal basis, the selected candidates will be placed in the appropriate category (viz. SC/ST/OBC/GEN) to which they belong.
Tuesday, November 17, 2009
Huge Requirement for IBM
Posted by R BANDARU at 4:05 PM
Contact Person: (Find mail id's near corresponding JobCode)
Contact #: -
Note - Only short-listed candidates will be called for the interview
Contact #: -
Skill & Job Description | GOM Code | Relevant Experience | Total Experience | Joining Location | Interview Location |
SAP FICO Brief Job Description: Candidates would be required to provide functional expertise within SAP, specifically in any of the modules FICO/TR. The ideal candidate should have spent around 2 years with minimum two full cycle implementations in the specific SAP module and should have good communication skills. He/She should also have had around 3-4 years' experience in a functional capacity. All projects are based in India. All Business Consulting positions will require extensive travelling on project sites in India. | GBS-0229454 | 4 years | 7 years | Will be communicated post candidate screening and selection | Will be communicated post candidate screening and selection |
SAP MM Brief Job Description: The candidates would be required to provide functional expertise within SAP, specifically in the any of the modules MM / WM / QM.* The ideal candidate should have spent around 2 years with minimum 2 full cycle implementations in the specific SAP module, and should possess good communication skills .He/She should also have had around 3-4 years' experience in a functional capacity. All projects are based in India. All Business Consulting positions will require extensive travelling on project sites in India . | GBS-0229456 | 4 years | 7 years | Will be communicated post candidate screening and selection | Will be communicated post candidate screening and selection |
SAP EP Brief Job Description: The candidates would be required to provide functional expertise within SAP . The ideal candidate should have spent around 3 years with minimum 2 full cycle implementations in the specific SAP module and have good communication skills. He/She should also have had around 4 years' experience in functional capacity. All projects are based in India . All business consulting positions will require extensive travelling on project sites in India. | GBS-0229451 | 3 years | 6 years | Will be communicated post candidate screening and selection | Will be communicated post candidate screening and selection |
SAP PM Brief Job Description: The candidate would be required to provide functional expertise within SAP. The ideal candidate should have spent around 2 years with minimum 2 full-cycle implementations in the specific PM module, and should possess good communication skills. He/She should also have had around 4 years' experience in functional capacity. All projects are based in India. All business consulting positions will require extensive travelling on project sites in India. | GBS-0229439 | 3 years | 6 years | Will be communicated post candidate screening and selection | Will be communicated post candidate screening and selection |
Note - Only short-listed candidates will be called for the interview
Note -
|
Note - Shortlisted candidates will be called for the interview. |
|
Subscribe to:
Posts (Atom)