Thursday, September 24, 2009
Wednesday, September 23, 2009
Sales Executive- University Program
Sales Executive– University Program
Position Senior/Sales Executive
Location Pune
Qualification
B.Sc., Diploma, BE/ B.Tech (Electronics and Communication)
Experience 2+ Years
Skillsets
* Should be familiar with the local language of the respective Location (Bangalore, Chennai).
* Evaluation of business potential of education market segments. Should have knack of sales.
* Responsible for tapping different institutions for the sales of EDA products like Mentor Graphics, Xilinx etc.
* Taking up challenging assignments.
Key Performance Areas
1. Pre-Sale technical discussions with clients to gain an understanding of the requirement and ensure effective Conversion.
2. Grow revenue at each of assigned account.
3. Participation in Global Training programs effectively.
Tasks and Responsibilities
* To analyse market trends, customer requirements and accordingly channelise marketing activities.
* Responsible for Product Positioning, Brand strategizing through various marketing activities like Seminars, Presentations, Campaigns, Technical workshops.
* Account Management - Client communication throughout the sales cycle that includes activities like RFP/RFQ generation.
* Handle various Corporate Presentations involving senior Management personnel.
* Responsible for coordinating with Field Application Engineers & involved in customer Pre & Post sale consultation.
* Lead/ prospect generation, qualification, distribution, tracking, analysis, reporting, meeting planning, proposal generation & support.
Pls send me your Resume,if any body interestd.
Position Senior/Sales Executive
Location Pune
Qualification
B.Sc., Diploma, BE/ B.Tech (Electronics and Communication)
Experience 2+ Years
Skillsets
* Should be familiar with the local language of the respective Location (Bangalore, Chennai).
* Evaluation of business potential of education market segments. Should have knack of sales.
* Responsible for tapping different institutions for the sales of EDA products like Mentor Graphics, Xilinx etc.
* Taking up challenging assignments.
Key Performance Areas
1. Pre-Sale technical discussions with clients to gain an understanding of the requirement and ensure effective Conversion.
2. Grow revenue at each of assigned account.
3. Participation in Global Training programs effectively.
Tasks and Responsibilities
* To analyse market trends, customer requirements and accordingly channelise marketing activities.
* Responsible for Product Positioning, Brand strategizing through various marketing activities like Seminars, Presentations, Campaigns, Technical workshops.
* Account Management - Client communication throughout the sales cycle that includes activities like RFP/RFQ generation.
* Handle various Corporate Presentations involving senior Management personnel.
* Responsible for coordinating with Field Application Engineers & involved in customer Pre & Post sale consultation.
* Lead/ prospect generation, qualification, distribution, tracking, analysis, reporting, meeting planning, proposal generation & support.
Pls send me your Resume,if any body interestd.
CAD Engineer - PCB Design @ Kyocera, Bangalore
CAD Engineer - PCB Design
Kyocera Wireless (India) Pvt Ltd. - Bangalore, KA
See original job posting at Naukri.com »
Quick ApplyKyocera Wireless (India) Pvt Ltd. - Bangalore, KA
See original job posting at Naukri.com »
Customised Apply
If you are in wireless, discover the global champion that is serving some real hot aces - Kyocera Wireless. The place where cutting edge technology and best-in-class talent enable end-to-end product development. Our core technology supports Kyocera's global marketing strategies. The challenge is now to develop products for 2010 ... view or apply to job
From Naukri.com - 1 hour 24 minutes ago - save job - block
CAD Engineer - PCB Design
Kyocera Wireless (India) Pvt Ltd. - Bangalore, KA
to Wireless Network Systems. Designation CAD Engineer - PCB Design Job Description Responsible for CAD... Allegro software, PCB Design and CAD library creation...
From Naukri.com - 10:03 AM - save job, email, block, more...
Senior Engineer, Hardware - Phone design
Kyocera Wireless (India) Pvt Ltd. - Bangalore, KA
Senior Engineer, Hardware - Phone design Job... of phone design experience. 1. 2G/2.5G/3G handset design experience. Hardware design experience with...
From Naukri.com - 10:11 AM - save job, email, block, more...
Senior Engineer, Hardware - RF Board Design
Kyocera Wireless (India) Pvt Ltd. - Bangalore, KA
Senior Engineer, Hardware - RF Board Design Job... design and testing of W-CDMA transceiver RF board design and testing of WIFI transceiver RF board design...
From Naukri.com - 10:03 AM - save job, email, block, more...
Monday, September 21, 2009
Openings in AMD
HI All,
It is not only just referral fee , here is a chance to Win a Special Referral T – Shirt or Watch for your every successful referral and take pride . This Scheme is effective for all new hires who have joined from July 09 onwards.( i.e employee who have referred July new hires)
Mail your CV to Team HR: Vennu Srinivaskumar / K.Aravinth( srinivaskumar.vennu@amd.com / aravinth.krishnamurthy@amd.com )
Please find our list of current opening at Hyderabad.
A. MTS- ASIC/Layout Design Engineer - GSE Team ( Hiring Manager- Nuti Srinivas/ Lotti Vijay Kumar/ Zakir/ Edara Sagar)
• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering
• Minimum 7+ years experience in ASIC Design Verification, including 2 years as a verification lead
• At least 2+ years experience in complex ASIC Design Verification, direct experience in SOC or Processor/Graphics/Video is preferred
• Must have excellent knowledge of ASIC Design Flow
• Extensive experience with C & C++ and SystemC
• Experience in developing complex testbench/model in verilog, PLI and/or System verilog
• Excellent debug skills in both functional and gate level simulations are must.
• Experience in random test generation, coverage analysis, failure debug, formal equivalency checking, and Assertions (PSL, SVA)
• Proficiency in common UNIX scripting languages (perl, csh, sh.)
• Knowledge of I/O interfaces like USB2.0, SATA, SD and etc is desired
• Knowledge of 2D/3D Graphics, Video and Display standards is a plus
• Must have good communication skills and the ability and desire to foster a team environment.
• Minimum 4+ years experience in ASIC Design Verification
• Experience in developing complex testbench/model in verilog, System verilog or SystemC
• Experience with coverage-based verification methodology
• Experience in writing testplans and testcases
• Excellent debug skills in both functional and gate level simulations are must.
• Experience in random test generation, coverage analysis, failure debug, formal equivalency checking, and Assertions (PSL, SVA)
• Strong Verilog, PLI interface, SystemC or C/C++, Perl/shell scripts or Vera programming skills.
• Experience with emulation based verification and/or simulation acceleration techniques an asset
• Must have good communication skills and the ability and desire to work as a team
C. Senior Software Development Engineer –Software Team ( Hiring Manager: Swaminathan Vasudevan/ Murali Krishna Kuppili)
· Install Shield - GPG
D. Design Engineer 2- PSE Team (Hiring Manager: Tarun Batra/ Sudhakar Kale)
· 3 - 5 yrs experience in ASIC/SOC design and verification
Exposure to processor verification is highly preferred
Must have taped-out at least one successful SOC
Appropriate candidate will have the skills of:
• Verilog/High level verification
• SOC verification and random test generation
• Testplanning & test writing especially for processor verification
• Exposure to tools like: VCS/NCSim, Debussy
• Perl and scripting
• Knowledge/exposure to complete SOC tape-out flow
E. Senior. Design Engineer- PSE Team (Hiring Manager: Tarun Batra/ Sudhakar Kale)
· 5 - 7 yrs experience in ASIC/SOC design and verification
Exposure to processor verification is highly preferred
Must have taped-out at least one successful SOC
Appropriate candidate will have the skills of:
• Verilog/High level verification
• SOC verification and random test generation
• Testplanning & test writing especially for processor verification
• Exposure to tools like: VCS/NCSim, Debussy
• Perl and scripting
• Knowledge/exposure to complete SOC tape-out flow
F. MTS- Design Engineer- PSE Team (Hiring Manager: Tarun Batra/ Sudhakar Kale)
· 7-10 yrs experience in ASIC/SOC design and verification
Exposure to processor verification is highly preferred
Must have taped-out at least one successful SOC
Appropriate candidate will have the skills of:
• Verilog/High level verification
• SOC verification and random test generation
• Testplanning & test writing especially for processor verification
• Exposure to tools like: VCS/NCSim, Debussy
• Perl and scripting
• Knowledge/exposure to complete SOC tape-out flow
G. MTS- Physical Design- PSE Team ( Hiring Manager- Pradeep Elamanchili/ Manoher Bommena)
· Key Responsibilities
· The position is for a PD staff engineer in the AMD PSE PD group catering to building the next generation fusion SoCs. Fusion programs will cater to the next gen compute requirements bringing in CPU, GPU, MC, Video and other misc functions on an integrated monolithic die. The candidate will technically lead and mentor a team of engineers on Physical Design (place and route ) duties both on block, as well as global top-level activities, which includes: top-level floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis, ECO tasks (timing, functional, noise based ECOs), power delivery etc. Good understanding required of all aspects of physical design taking a design from RTL/ Netlist to GDSII and production. In addition the candidate is expected to have close to expert level of skill in a few core areas.
· The candidates responsibilities will also include flow and methodology development related to the above tasks or new tasks that arise as technology changes. This involves flow design and implementation via coding in various languages. In addition, very strong communication skills and an ability to work in large groups are essential to being successful.
· Excellent debugging skills is a must, candidate must be more than a tool executor, and knows how to diagnose and devise workarounds for problems.
· Requirements
· Minimum 6 years of ASIC physical design experience.
· Leadership and Mentoring skills a must.
· Strong Back ground of ASIC Physical Design : Floor planning , P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.
· Hands on experience and detailed knowledge in Cadence or Synopsys or Magma ASIC Physical Design Tools
· Scripting Language with PERL ,TCL,AWK, shell scripting a very big asset.
· Familiar with Physical Verification is also desirable.
H. Senior ASIC/ Layout Design Engineer –PSE Team ( Hiring Manager- Pradeep Elamanchili/ Manoher Bommena)
· Key Responsibilities
· The position is for a Senior Physical Design Engineer in the AMD PSE PD group catering to building the next generation fusion SoCs. Fusion programs will cater to the next gen compute requirements bringing in CPU, GPU, MC, Video and other misc functions on an integrated monolithic die. In this position you will be responsible for the entire Physical implementation of our chips designed for PC, Handheld, Entertainment or DTV requirements. This position requires interface with large front-end design teams in US, Canada and India, mentoring new hires and owing an entire chip from inception to tapeout.
· The Sr. Physical Design Engineer will be responsible for 1. some full chip activities covering floor planning, clocking, budgeting, timing, verification etc., and/or 2. block level physical design activities for a given ASIC product, which includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks, power delivery solution development etc. In addition to this, he/she will also be participating in Physical design Flow development/upgrade by continuously working with the internal design teams and CAD vendors.
· The following is desirable:
Job Requirements:
It is not only just referral fee , here is a chance to Win a Special Referral T – Shirt or Watch for your every successful referral and take pride . This Scheme is effective for all new hires who have joined from July 09 onwards.( i.e employee who have referred July new hires)
Mail your CV to Team HR: Vennu Srinivaskumar / K.Aravinth( srinivaskumar.vennu@amd.com / aravinth.krishnamurthy@amd.com )
Please find our list of current opening at Hyderabad.
A. MTS- ASIC/Layout Design Engineer - GSE Team ( Hiring Manager- Nuti Srinivas/ Lotti Vijay Kumar/ Zakir/ Edara Sagar)
· Key Responsibilities:
• Responsible for participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy for the Graphics chips
• Specifying an overall design verification plan for an full chip SoC
• Specifying or reviewing plans for complex blocks within the ASIC
• Architecting new verification methodologies and evaluating new tools.
• Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes :
o self-checking, reusable, automated verification environment : both at full-chip & block level
o Constrained random generators and reference models
• Being a mentor and technical leader for more junior verification engineers.
• Leading or participating in the ASIC bring-up and debug
· Job Requirements and Skills:• Responsible for participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy for the Graphics chips
• Specifying an overall design verification plan for an full chip SoC
• Specifying or reviewing plans for complex blocks within the ASIC
• Architecting new verification methodologies and evaluating new tools.
• Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes :
o self-checking, reusable, automated verification environment : both at full-chip & block level
o Constrained random generators and reference models
• Being a mentor and technical leader for more junior verification engineers.
• Leading or participating in the ASIC bring-up and debug
• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering
• Minimum 7+ years experience in ASIC Design Verification, including 2 years as a verification lead
• At least 2+ years experience in complex ASIC Design Verification, direct experience in SOC or Processor/Graphics/Video is preferred
• Must have excellent knowledge of ASIC Design Flow
• Extensive experience with C & C++ and SystemC
• Experience in developing complex testbench/model in verilog, PLI and/or System verilog
• Excellent debug skills in both functional and gate level simulations are must.
• Experience in random test generation, coverage analysis, failure debug, formal equivalency checking, and Assertions (PSL, SVA)
• Proficiency in common UNIX scripting languages (perl, csh, sh.)
• Knowledge of I/O interfaces like USB2.0, SATA, SD and etc is desired
• Knowledge of 2D/3D Graphics, Video and Display standards is a plus
• Must have good communication skills and the ability and desire to foster a team environment.
B. Senior ASIC/Layout Design Engineer –GSE Team ( Hiring Manager- Nuti Srinivas/ Lotti Vijay Kumar/ Zakir/ Edara Sagar)
Key Responsibilities:
• Develop and document detailed test plans, block and system-level test benches and reference models
• Develop self-checking, reusable, automated verification environment : both at full-chip & block level
• Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports
• Create and analyze coverage metrics to ensure completeness
• Perform logic level and gate level simulations/regressions, analyzing test failures and aiding in debugging logic designs
• Setting up regression scripts, manage server farms, condense and present reports and improve verification environment
Job Requirements and Skills:
• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering Key Responsibilities:
• Develop and document detailed test plans, block and system-level test benches and reference models
• Develop self-checking, reusable, automated verification environment : both at full-chip & block level
• Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports
• Create and analyze coverage metrics to ensure completeness
• Perform logic level and gate level simulations/regressions, analyzing test failures and aiding in debugging logic designs
• Setting up regression scripts, manage server farms, condense and present reports and improve verification environment
Job Requirements and Skills:
• Minimum 4+ years experience in ASIC Design Verification
• Experience in developing complex testbench/model in verilog, System verilog or SystemC
• Experience with coverage-based verification methodology
• Experience in writing testplans and testcases
• Excellent debug skills in both functional and gate level simulations are must.
• Experience in random test generation, coverage analysis, failure debug, formal equivalency checking, and Assertions (PSL, SVA)
• Strong Verilog, PLI interface, SystemC or C/C++, Perl/shell scripts or Vera programming skills.
• Experience with emulation based verification and/or simulation acceleration techniques an asset
• Must have good communication skills and the ability and desire to work as a team
C. Senior Software Development Engineer –Software Team ( Hiring Manager: Swaminathan Vasudevan/ Murali Krishna Kuppili)
· Install Shield - GPG
4+ years of experience in developing applications using C++, MFC, ATL, COM.
2+ years of experience in developing MSI packages (Installshield preferable).
Experience in developing driver installations using DIFx Framework.
Good understanding of Windows Installer and Windows Driver Model.
Expert knowledge of Windows Operation systems (XP and Vista).
Ability to learn new things and should be a team player.
D. Design Engineer 2- PSE Team (Hiring Manager: Tarun Batra/ Sudhakar Kale)
· 3 - 5 yrs experience in ASIC/SOC design and verification
Exposure to processor verification is highly preferred
Must have taped-out at least one successful SOC
Appropriate candidate will have the skills of:
• Verilog/High level verification
• SOC verification and random test generation
• Testplanning & test writing especially for processor verification
• Exposure to tools like: VCS/NCSim, Debussy
• Perl and scripting
• Knowledge/exposure to complete SOC tape-out flow
E. Senior. Design Engineer- PSE Team (Hiring Manager: Tarun Batra/ Sudhakar Kale)
· 5 - 7 yrs experience in ASIC/SOC design and verification
Exposure to processor verification is highly preferred
Must have taped-out at least one successful SOC
Appropriate candidate will have the skills of:
• Verilog/High level verification
• SOC verification and random test generation
• Testplanning & test writing especially for processor verification
• Exposure to tools like: VCS/NCSim, Debussy
• Perl and scripting
• Knowledge/exposure to complete SOC tape-out flow
F. MTS- Design Engineer- PSE Team (Hiring Manager: Tarun Batra/ Sudhakar Kale)
· 7-10 yrs experience in ASIC/SOC design and verification
Exposure to processor verification is highly preferred
Must have taped-out at least one successful SOC
Appropriate candidate will have the skills of:
• Verilog/High level verification
• SOC verification and random test generation
• Testplanning & test writing especially for processor verification
• Exposure to tools like: VCS/NCSim, Debussy
• Perl and scripting
• Knowledge/exposure to complete SOC tape-out flow
G. MTS- Physical Design- PSE Team ( Hiring Manager- Pradeep Elamanchili/ Manoher Bommena)
· Key Responsibilities
· The position is for a PD staff engineer in the AMD PSE PD group catering to building the next generation fusion SoCs. Fusion programs will cater to the next gen compute requirements bringing in CPU, GPU, MC, Video and other misc functions on an integrated monolithic die. The candidate will technically lead and mentor a team of engineers on Physical Design (place and route ) duties both on block, as well as global top-level activities, which includes: top-level floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis, ECO tasks (timing, functional, noise based ECOs), power delivery etc. Good understanding required of all aspects of physical design taking a design from RTL/ Netlist to GDSII and production. In addition the candidate is expected to have close to expert level of skill in a few core areas.
· The candidates responsibilities will also include flow and methodology development related to the above tasks or new tasks that arise as technology changes. This involves flow design and implementation via coding in various languages. In addition, very strong communication skills and an ability to work in large groups are essential to being successful.
· Excellent debugging skills is a must, candidate must be more than a tool executor, and knows how to diagnose and devise workarounds for problems.
· Requirements
· Minimum 6 years of ASIC physical design experience.
· Leadership and Mentoring skills a must.
· Strong Back ground of ASIC Physical Design : Floor planning , P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.
· Hands on experience and detailed knowledge in Cadence or Synopsys or Magma ASIC Physical Design Tools
· Scripting Language with PERL ,TCL,AWK, shell scripting a very big asset.
· Familiar with Physical Verification is also desirable.
H. Senior ASIC/ Layout Design Engineer –PSE Team ( Hiring Manager- Pradeep Elamanchili/ Manoher Bommena)
· Key Responsibilities
· The position is for a Senior Physical Design Engineer in the AMD PSE PD group catering to building the next generation fusion SoCs. Fusion programs will cater to the next gen compute requirements bringing in CPU, GPU, MC, Video and other misc functions on an integrated monolithic die. In this position you will be responsible for the entire Physical implementation of our chips designed for PC, Handheld, Entertainment or DTV requirements. This position requires interface with large front-end design teams in US, Canada and India, mentoring new hires and owing an entire chip from inception to tapeout.
· The Sr. Physical Design Engineer will be responsible for 1. some full chip activities covering floor planning, clocking, budgeting, timing, verification etc., and/or 2. block level physical design activities for a given ASIC product, which includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks, power delivery solution development etc. In addition to this, he/she will also be participating in Physical design Flow development/upgrade by continuously working with the internal design teams and CAD vendors.
· The following is desirable:
Ø Understanding Verilog HDL
Ø Understanding Deep Submicron effects such as 90nm and below
Ø Understanding OCV, DFM, DFY
Ø Excellent Block level and Fullchip level Timing closure skills
Ø Displaying motivation, leadership skills and working in teams
Job Requirements:
Ø Minimum 4 year of ASIC physical design experience.
Ø Reasonable Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.
Ø Hands on experience and reasonable knowledge in Cadence and Synopsys Physical Implementation Tools
Ø Should have participated in a minimum of 3-4 fullchip tapeouts.
Ø Scripting Language with PERL, TCL, AWK, shell scripting is highly desirable.
Ø Familiar with Physical Verification will be a plus.
Team HR.
AMD
great opportunity for work experience seekers
Hi,
Here is a great opportunity for work experience seekers.
IT-Anubhav helps the enthusiastic people to get hands on work experience which will kick start their career.
At IT_Anubhav,
You will think and analyze the problem,
Put in your thoughts to solve the problem,
Know and learn from your mistakes,
Learn to work independently as well as in a group
and get valuable suggestions by your guides(having 3-30 yrs of EXP).
It is a very good opportunity to get a work experience and to know how and why experience matters in the industry.
IT-Anubhav provides project work and work experience to M Tech students as well as people who are interested in getting hands on experience in commercial projects.
Please visit http://www.itseers.com/it-
Note : Please forward this to your contacts.
HR
IT-Anubhav
9448047407
it-anubhav@itseers.com
Here is a great opportunity for work experience seekers.
IT-Anubhav helps the enthusiastic people to get hands on work experience which will kick start their career.
At IT_Anubhav,
You will think and analyze the problem,
Put in your thoughts to solve the problem,
Know and learn from your mistakes,
Learn to work independently as well as in a group
and get valuable suggestions by your guides(having 3-30 yrs of EXP).
It is a very good opportunity to get a work experience and to know how and why experience matters in the industry.
IT-Anubhav provides project work and work experience to M Tech students as well as people who are interested in getting hands on experience in commercial projects.
Please visit http://www.itseers.com/it-
Note : Please forward this to your contacts.
HR
IT-Anubhav
9448047407
it-anubhav@itseers.com
Friday, September 18, 2009
Job Openings [[18 Sep 09]]
Circuit Designer B.Tech/B.E
Job Description
Good Academic experience in Full-Custom/Memory/Analog-Mixed Signal Circuit Design
Simulation exp. on HSPICE/SPECTRE/ELDO
Deep Understanding of fundamentals of VLSI
MUST have strong academic background (min 70% throughout)
Desired Candidate Profile
0-1 Years of experience
B.Tech/BE/M.Tech/MS in ELECTRONICS (From reputed institutes)
MUST HAVE STRONG ACADEMIC BACKGROUND (MIN 70% throughout)
Proactive and self-motivated.
Good communication skill.
Company Profile
Masamb provides services including IP enabled services to Semiconductor, EDA and OEM companies in RTL Design, Functional Verification, AMS Design, Physical Design, CAD Methodology and Real Time Embedded / Firmware applications development.
Contact Details
Company Name : Masamb Electronics Systems Private Limited.
Website : http://www.masamb.com
Executive Name : HR
Email Address : hr@masamb.com
Junior Software Developer - MS Technologies
Job Description
Position: Junior Software Developer
Requirements:
• Knowledge and experience in C# ,ASP.NET SQL and XML (academic project in NET is Must)
• Experience working in a variety of team sizes and excellent communication and interpersonal skills.
Desired Candidate Profile
We are looking to add a Junior Developer to our Engineering Team to assist in application development and daily operations. With a variety of coding languages and platforms, it is a challenging position that requires a desire to learn.
Company Profile
Honeypot IT Consulting Private Limited is an internationally established software development company with offices USA and India. The Indian office and development centre is located in a state-of-art facility in the heart of Hyderabad, India.
Contact Details
Company Name:Honeypot IT
Website:http://www.honeypotit.com
Address:
# 6-2-45/11, Advocates Colony, AC Guards,
HYDERABAD,Andhra Pradesh,India 500004
Email Address : hr@honeypotit.com
Dorf Ketal Chemicals India Pvt Ltd
Job Description
Job Profile
Application Related Work
Working on Projects for Polymer
Day to day function of R&D Lab
Product Development
Education Qualification
B.Sc Chemistry freshers or with 1 to 2 years of Experience in research lab
Location
MIDC Taloja - Navi Mumbai
Desired Candidate Profile
B.Sc Freshers or 1-2 years of similar experience in chemical industry in Research department.
Company Profile
Dorf Ketal Chemicals is a speciality chemicals company with key business in Refinery Process Chemicals, Petrochemical process chemical, fuel additives, plastic additives & water treatment chemical. With a manufacturing plant in Taloja India and blending plants in US & Brazil, the Company is set to aggressively grow in both domestic and international markets. An ISO 9001 & 14001 company, Dorf Ketal Chemical's manufacturing operation is fully integrated with the entire value chain from global procurement. Dorf Ketal was awarded the most emerging company in the Pharma and Chemical sector for the year 2005, the award is instituted by CNBC, ICICI & CRISIL.
The company is professionally managerd, harnessing the best of technologies and people capabilities for its aggressive growth.
Dorf Ketal is the market leader for process chemicals for Refineries and Petrochemicals. Dorf Ketal Chemicals has identified Water Treatment as key growth driver for the coming years.
Contact Details
Company Name:
Dorf Ketal Chemicals India Pvt Ltd
Website:
http://www.dorfketal.com
http://jobsearch.naukri.com/mynaukri/mn ... 0909000209
Quad One Technologies Pvt. Ltd.
Job Description
Object Oriented Web application development using LAMP technologies and latest open source frameworks and technologies like CMS, Ajax, Smarty, JQuery.
Desired Candidate Profile
Candidates with 0 to 2 years of experience required. Candidates should have knowledge of LAMP technologies. Should have trained or worked in LAMP environment previously.
Company Profile
Quad One Technologies is a 8 year old Hyderabad based Software development and remote infrastructure management companies specializing is providing IT Infrastructure Management Services to the Financial Services industry
Contact Details
Company Name:Quad One Technologies Pvt. Ltd.
Website:http://www.quadone.com
Email Address : esantosh@quadone.com
BSF-Rs.15600-39100
Directorate General Border Security Force (BSF)
Recruitment of Assistant Commandant (Works/ Electrical)
BSF, invites application from the Male and Female Indian citizens for the post of Assistant Commandant Name of post No. of posts Qualification Pay Scale Age as on 12-10-2009
Assistant Commandant (Works) 4 B.E/ B.Tech (Civil) Rs.15600-39100 21-26 years
Assistant Commandant (Electrical) 4 B.E/ B.Tech (Electrical)
Physical Standards: Men Women
Height 165cm 157cm
Chest Unexpanded:81
Expanded :86 Well developed
Weight 50kg Proportional to height, but not less than 46 kg
Eye Sight: Distant Vision 6/6, 6/12 or 6/9, 6/9, Near Vision: J-I, J-II
How to apply
Applications filled in the prescribed format along with the attested copies of certificates in proof of age, qualification, caste and a DD of Rs.100 as exam fee remitted in favour of DDO Head Quarter Dg BSF payable at SBI Service Branch, New Delhi Code No.7687 should send at the address The Commandant(SSb), HQ DG BSF, Block No.10, CGO Complex, Lodhi Road, New Delhi-110003 on or before 12th October 2009. No fees for SC/ST and departmental candidates. Three passport size photograph attested by a gazette officer, one should be pasted on application form, one on admit card and the other should be kept in record. Also two self addressed envelops of size 25x12cms stamped Rs.27 should be attached in the application form. The envelop containing application should be super scribed with" Application for the Post of Assistant Commandant (Works/ Electrical) in BSF.
Click Here For details & Application Form
http://www.bsf.nic.in/recruitment/r251.pdf
Job Description
Good Academic experience in Full-Custom/Memory/Analog-Mixed Signal Circuit Design
Simulation exp. on HSPICE/SPECTRE/ELDO
Deep Understanding of fundamentals of VLSI
MUST have strong academic background (min 70% throughout)
Desired Candidate Profile
0-1 Years of experience
B.Tech/BE/M.Tech/MS in ELECTRONICS (From reputed institutes)
MUST HAVE STRONG ACADEMIC BACKGROUND (MIN 70% throughout)
Proactive and self-motivated.
Good communication skill.
Company Profile
Masamb provides services including IP enabled services to Semiconductor, EDA and OEM companies in RTL Design, Functional Verification, AMS Design, Physical Design, CAD Methodology and Real Time Embedded / Firmware applications development.
Contact Details
Company Name : Masamb Electronics Systems Private Limited.
Website : http://www.masamb.com
Executive Name : HR
Email Address : hr@masamb.com
Junior Software Developer - MS Technologies
Job Description
Position: Junior Software Developer
Requirements:
• Knowledge and experience in C# ,ASP.NET SQL and XML (academic project in NET is Must)
• Experience working in a variety of team sizes and excellent communication and interpersonal skills.
Desired Candidate Profile
We are looking to add a Junior Developer to our Engineering Team to assist in application development and daily operations. With a variety of coding languages and platforms, it is a challenging position that requires a desire to learn.
Company Profile
Honeypot IT Consulting Private Limited is an internationally established software development company with offices USA and India. The Indian office and development centre is located in a state-of-art facility in the heart of Hyderabad, India.
Contact Details
Company Name:Honeypot IT
Website:http://www.honeypotit.com
Address:
# 6-2-45/11, Advocates Colony, AC Guards,
HYDERABAD,Andhra Pradesh,India 500004
Email Address : hr@honeypotit.com
Dorf Ketal Chemicals India Pvt Ltd
Job Description
Job Profile
Application Related Work
Working on Projects for Polymer
Day to day function of R&D Lab
Product Development
Education Qualification
B.Sc Chemistry freshers or with 1 to 2 years of Experience in research lab
Location
MIDC Taloja - Navi Mumbai
Desired Candidate Profile
B.Sc Freshers or 1-2 years of similar experience in chemical industry in Research department.
Company Profile
Dorf Ketal Chemicals is a speciality chemicals company with key business in Refinery Process Chemicals, Petrochemical process chemical, fuel additives, plastic additives & water treatment chemical. With a manufacturing plant in Taloja India and blending plants in US & Brazil, the Company is set to aggressively grow in both domestic and international markets. An ISO 9001 & 14001 company, Dorf Ketal Chemical's manufacturing operation is fully integrated with the entire value chain from global procurement. Dorf Ketal was awarded the most emerging company in the Pharma and Chemical sector for the year 2005, the award is instituted by CNBC, ICICI & CRISIL.
The company is professionally managerd, harnessing the best of technologies and people capabilities for its aggressive growth.
Dorf Ketal is the market leader for process chemicals for Refineries and Petrochemicals. Dorf Ketal Chemicals has identified Water Treatment as key growth driver for the coming years.
Contact Details
Company Name:
Dorf Ketal Chemicals India Pvt Ltd
Website:
http://www.dorfketal.com
http://jobsearch.naukri.com/mynaukri/mn ... 0909000209
Quad One Technologies Pvt. Ltd.
Job Description
Object Oriented Web application development using LAMP technologies and latest open source frameworks and technologies like CMS, Ajax, Smarty, JQuery.
Desired Candidate Profile
Candidates with 0 to 2 years of experience required. Candidates should have knowledge of LAMP technologies. Should have trained or worked in LAMP environment previously.
Company Profile
Quad One Technologies is a 8 year old Hyderabad based Software development and remote infrastructure management companies specializing is providing IT Infrastructure Management Services to the Financial Services industry
Contact Details
Company Name:Quad One Technologies Pvt. Ltd.
Website:http://www.quadone.com
Email Address : esantosh@quadone.com
BSF-Rs.15600-39100
Directorate General Border Security Force (BSF)
Recruitment of Assistant Commandant (Works/ Electrical)
BSF, invites application from the Male and Female Indian citizens for the post of Assistant Commandant Name of post No. of posts Qualification Pay Scale Age as on 12-10-2009
Assistant Commandant (Works) 4 B.E/ B.Tech (Civil) Rs.15600-39100 21-26 years
Assistant Commandant (Electrical) 4 B.E/ B.Tech (Electrical)
Physical Standards: Men Women
Height 165cm 157cm
Chest Unexpanded:81
Expanded :86 Well developed
Weight 50kg Proportional to height, but not less than 46 kg
Eye Sight: Distant Vision 6/6, 6/12 or 6/9, 6/9, Near Vision: J-I, J-II
How to apply
Applications filled in the prescribed format along with the attested copies of certificates in proof of age, qualification, caste and a DD of Rs.100 as exam fee remitted in favour of DDO Head Quarter Dg BSF payable at SBI Service Branch, New Delhi Code No.7687 should send at the address The Commandant(SSb), HQ DG BSF, Block No.10, CGO Complex, Lodhi Road, New Delhi-110003 on or before 12th October 2009. No fees for SC/ST and departmental candidates. Three passport size photograph attested by a gazette officer, one should be pasted on application form, one on admit card and the other should be kept in record. Also two self addressed envelops of size 25x12cms stamped Rs.27 should be attached in the application form. The envelop containing application should be super scribed with" Application for the Post of Assistant Commandant (Works/ Electrical) in BSF.
Click Here For details & Application Form
http://www.bsf.nic.in/recruitment/r251.pdf
Wednesday, September 16, 2009
Freshers Required!!!
Hi
Hope you are doing great!
We have urgent requirement for Freshers with better communication skills, who are looking for better oppurtunites in Hyderabad location.
Qualification: 10+2, Bsc, Bcom, B.ET /B.Tech, MBA (Marketing)
Job Location: Hyderabad.
Interested candidates, please contact to 9000789663.
You can share this requriement with your friends and colleagues.
Regards,
Vinay
HR Team.
Hyderabad.
Hope you are doing great!
We have urgent requirement for Freshers with better communication skills, who are looking for better oppurtunites in Hyderabad location.
Qualification: 10+2, Bsc, Bcom, B.ET /B.Tech, MBA (Marketing)
Job Location: Hyderabad.
Interested candidates, please contact to 9000789663.
You can share this requriement with your friends and colleagues.
Regards,
Vinay
HR Team.
Hyderabad.
Wanted Trainees/Engineers ..Talent Acquisition Team
Dear Associates,
Make your friend your buddy at work too - refer him/her to XIUS-bcgi
We are conducting a Walk-in Drive for Trainees/Software Engineers on Saturday, 19th Sept '09.
Ground Rules for the Walk-in:
Please Walk-in with a copy of your most updated CV and last salary slip for Interview.
Kindly ask your references to mention your name and Ecode on top of the Resume for this walk-in.
We are conducting a Walk-in Drive for Trainees/Software Engineers on Saturday, 19th Sept '09.
Ground Rules for the Walk-in:
Please Walk-in with a copy of your most updated CV and last salary slip for Interview.
Kindly ask your references to mention your name and Ecode on top of the Resume for this walk-in.
Address:
Megasoft Towers
6-3-1192/2/1,
Kundanbagh, Begumpet,
Hyderabad.
ELIGIBILITY CRITERIA : MUST
Reach the Walk-in venue on time as per schedule, along with all the necessary documents.
Time : 10:00 AM for the Written Test. Further briefing at the venue on 19th Sept. Please come prepared to be available for the entire day.
Try to reach the venue early in the morning at 10:00 AM in order to avoid rush and inconvenience. Selected candidates would be offered on the same day.
Megasoft Towers
6-3-1192/2/1,
Kundanbagh, Begumpet,
Hyderabad.
Tel: 040-40330000
Opportunities available for Trainees/Software Engineers (30 Positions)
TECH SKILLS REQUIRED :- C, C++, Java, SQL and PL/SQL
- OS: Unix / Linux
Job Description : Responsible for development/ support/ maintenance/ implementation of small non-complex components of a project module. Works on problems of limited scope, through usage of standard programming concepts and principles. Works under supervision/ guidance with frequent review of accomplished objectives. Candidates would develop domain knowledge along with technical/ proprietary skills, on the job.
ELIGIBILITY CRITERIA : MUST
- Candidates upto 2 years (only) of experience in the above areas.
- Educational Qualification: Engineering Graduates passed out in last three years only (after 2006) with 60% and above aggregate.
- FRESHERS would be considered for a Trainee position.
Time : 10:00 AM for the Written Test. Further briefing at the venue on 19th Sept. Please come prepared to be available for the entire day.
Try to reach the venue early in the morning at 10:00 AM in order to avoid rush and inconvenience. Selected candidates would be offered on the same day.
Contact Person: Sr. Executive-Talent Acquisition, Mr.Rakesh Nair (Ext. 8287) and Deputy Manager- Talent Acquisition, Ms.Sarita Narisetty (Ext. 8249).
You are eligible to claim referral fee as per the HR policy. Regards,
Talent Acquisition Team
XIUS-bcgi
(O) 040-40330000 Ext: 8287/8249
ImmediateRequirement for Fresh Graduates! [Keane]
ImmediateRequirement for Fresh Graduates!  |
Dear Keane Colleagues, We are pleased to announce competitive positions within Keane’s Testing practice. As you are aware, it is critical to obtain the appropriate experience and skill mix in our new hires. Only with the right level of expertise can we ensure excellence in delivery and complete customer satisfaction. We invite you to refer your friends and acquaintances who meet the criteria for the following position: Immediate Requirement for fresh graduates - BCA, BSc (Computers/IT/Electronics), 3 year Diploma (Computers/IT/Electronics) - Candidates with Excellent communication skills. - First class academic record, 0-1 year experience, willingness to work anywhere in India. All referrals are covered by the referral policy. For details of the policy and the corresponding referral bonuses, visit your policies home page. Please email CVs to campus.hiring@keane.com with the corresponding job description in the subject line of your mail. Kind regards, Campus Team |
Copyrights © 2009, Keane. All rights reserved. |
Tuesday, September 15, 2009
Excellent Opportunity for freshers
*From:* Kavitha NARAYAN [mailto:kavitha.subcon@stericsson.com]
*Subject:* Inviting Freshers profiles
Dear All,
We would like to get some freshers to ST Ericsson through your referrals.
Criteria:
Please send all your referrals by tomorrow (Wednesday) 2pm.
Regards,
Kavitha Narayan
HR
*Subject:* Inviting Freshers profiles
Dear All,
We would like to get some freshers to ST Ericsson through your referrals.
Criteria:
- 75% aggregate
- BE - CS, IS, IT, EEE, E&C & Multi Media
- 2007-2008 and above pass out.
- Excellent communication and good presentation skills.
Please send all your referrals by tomorrow (Wednesday) 2pm.
Regards,
Kavitha Narayan
HR
Jobs for Diploma Candidates..
Hello Friends,
Plz let me know if u have any one who are doing their Final year diploma ECE or EEE (not 2009 pass outs). If so plz forward their resumes to Thulasiram.A@kpitcummins.com
Plz let me know if u have any one who are doing their Final year diploma ECE or EEE (not 2009 pass outs). If so plz forward their resumes to Thulasiram.A@kpitcummins.com
Walk-In @ Honeywell on 19 sept 2009(2-5 yrs exp in C & C++)... To those who are in Banglore...
Walk-In @ Honeywell on 19 sept 2009(2-5 yrs exp in C & C++)... To those who are in Banglore..
For Details: http://www.chetanasforum.com/
New Openings..
This is the blog where you can find latest job openings for the all the Diploma/Graduates/Post Graduates/..any one who are seeking for the jobs.
Feel free to comment/post If you knew openings.
Thanks,
Moderator.
Feel free to comment/post If you knew openings.
Thanks,
Moderator.
Saturday, August 15, 2009
Jobs Archieve
Urgent requiremen
DATE: 11 SEP 2009
Dear all,
We have urgent requirement of SQL DBAs and we need to close these positions ASAP. Kindly refer your friends, relatives, acquaintances, ex-colleagues, batch mates etc… Your referrals will fetch you great bounties, details of which are mentioned as under:
Sl.No | Position | Bounty |
1 | SQL DBA | Rs. 25,000/- |
Job description:
Position – SQL DBA
Experience – 4 years to 7 years
Essential skills/experience:
DBA Skill set:
• IT professional having 4+ years hands on experience as MSSQL Server DBA
• worked in 24x7 production support environment
• Expertise in SQL Server installations (2000/2005)
• Database migration
• log shipping, clustering, backup and recovery
• Remote DBA Production support for MSSQL Database Servers
• Perform proactive database maintenance work on a scheduled basis
• Perform SQL Database migrations from SQL 2000 – 2005 version
• Troubleshooting and fixing database related errors
• Maintaining Users and Resources, Database Security documentations
• Installation & Configuration of MSSQL Server 2000 and 2005
• Installation of MSSQL Server on Microsoft Cluster Servers SQL 2000 and SQL 2005 Server
• Database migration and SQL Server version upgrades
• Database and SQL query performance fine tuning
• Performance monitoring and System fine Tuning
• Certifications: MCDBA/MCP of SQL Server
• RDBMS: MSSQL Server 2000, 2005
DB Development skill set:
• Database Development with MS SQL 2000/2005.
• Strong experience in database access methodologies.
• Data modeling including a complete understanding of all normalized forms design, ER Modeling and industry design standards.
• Design and development of stored procedures, triggers and queries in T-SQL.
• Knowledge of integrating SQL Server db solutions in .NET environments, with working knowledge of C#, VB.NET, ASP.NET and SOA with web services.
BI Skill Set:
• Good experience on data-warehousing (*must)
• Exceptional SSIS/ETL program designers and coders using multiple transforms into multiple Data warehousing environments (e.g. DEV, TEST, PROD).
• Experience with Microsoft Reporting and Analysis Services.
• Able to quickly analyze and understand existing dimensional and relational Databases, and the ETL and SQL that populate them.
• Exceptional SQL designers and coders.
• Hands-on experience in designing and coding high-volume DTS or ETL (SSIS) type SQL applications for efficiency and maintainability.
Process for submitting the resume/s & availing the bounty:
- Please send the profiles to Suraj Sharma (suraj.sharma@valuelabs.net).
- Mention your name, Emp. ID and project in the email without fail.
- The last date for intake of resumes is 14th Sep, 09.
- The resumes will be screened by the technical panel and the short-listed candidates will be considered for the selection process.
- In either case, employees will be posted on the status of the resume submitted.
- Once the candidate/s joins, you (associate who has referred the candidate) will get the bounty within one month from his/her date of joining. Needless to say the associate referred and the new joinee have to be associated with the company.
Like always, we need your co-operation in filling these positions and aiding in the growth of ValueLabs…
PS: Please note that this special bounty is applicable only for the above mentioned position.
Best regards
Team HR
(Talent Acquisition Group)
DATE :09Sep 2009
DATE : 05 SEP 09 Walk In Interview for C#, C++, SQL and .NET Framework |
| Mode of Interview – Written Test Date of Test – 5th Sep 09 Time – 10am Venue – Mother Earth, Kalyani Campus Bannerghatta Road *Candidates to carry a copy of their resume and Name, EID and Emp ID of the referee Skills - .Net framework, C#, SQL and C++ Position – Developer/ Sr. Developer Years of experience – 2 – 4years only Description • Excellent working knowledge on C++, C# and .net framework • Excellent working knowledge on SQL Server, TSQL programming, SQL Server Performance and maintenance. • Working knowledge on Web Servers (IIS) deployment scenarios. • Working knowledge on Crystal Reports development and deployment. • Knowledge on Sliver light application development. • Knowledge on Business Objects • Knowledge required on BI (Business Intelligent) Applications. |
Hi Guys,
Above given are the details of the Walkin-Interview at Honeywell. Please comedown if you are interested. Also, forward it to your friends and check whether anybody is interested.
*Candidates will have to give the following information to our HR while coming for interview
Referee Name: Ranjith Keloth
EID: E464864
Emp ID: 8754
Tuesday, August 11, 2009
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