Openings @ AMD

Contact Person:Vennu SrinivasKumar / K. Aravinth / Manju  ( Srinivas Vennu (or) Krishna Murthy;(or) Manju Mandali)
Contact #:  --

We are planning to conduct Walk In Interviews at Bangalore office on Sunday 22^nd November for the below positions.

Skills in Short

ü  Physical Design                 : Place & route, synthesis, Timing, Clock   = 3 to 15 yrs of experience for Various Level

ü  Verification                           :  4 to 9 years of experience

ü  DFT Implementation          :  4+ yrs onwards

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Detailed Job Description.

A.   MTS- ASIC/Layout Design Engineer -  GSE Team ()

·         Key Responsibilities:
• Responsible for participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy for the Graphics chips
• Specifying an overall design verification plan for an full chip SoC
• Specifying or reviewing plans for complex blocks within the ASIC
• Architecting new verification methodologies and evaluating new tools.
• Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes :
o self-checking, reusable, automated verification environment : both at full-chip & block level
o Constrained random generators and reference models
• Being a mentor and technical leader for more junior verification engineers.
• Leading or participating in the ASIC bring-up and debug

·         Job Requirements and Skills:
• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering
• Minimum 7+ years experience in ASIC Design Verification, including 2 years as a verification lead
• At least 2+ years experience in complex ASIC Design Verification, direct experience in SOC or Processor/Graphics/Video is preferred
• Must have excellent knowledge of ASIC Design Flow
• Extensive experience with C & C++ and SystemC
• Experience in developing complex testbench/model in verilog, PLI and/or System verilog
• Excellent debug skills in both functional and gate level simulations are must.
• Experience in random test generation, coverage analysis, failure debug, formal equivalency checking, and Assertions (PSL, SVA)
• Proficiency in common UNIX scripting languages (perl, csh, sh.)
• Knowledge of I/O interfaces like USB2.0, SATA, SD and etc is desired
• Knowledge of 2D/3D Graphics, Video and Display standards is a plus
• Must have good communication skills and the ability and desire to foster a team environment.

B.   Senior. Design Engineer- PSE Team ()

·         5 - 7 yrs experience in ASIC/SOC design and verification

Exposure to processor verification is highly preferred

Must have taped-out at least one successful SOC

Appropriate candidate will have the skills of:
• Verilog/High level verification
• SOC verification and random test generation
• Testplanning & test writing especially for processor verification
• Exposure to tools like: VCS/NCSim, Debussy
• Perl and scripting
• Knowledge/exposure to complete SOC tape-out flow

          

C.   MTS- Physical Design- PSE Team ()

·         Key Responsibilities

·         The position is for a PD staff engineer in the AMD PSE PD group catering to building the next generation fusion SoCs. Fusion programs will cater to the next gen compute requirements bringing in CPU, GPU, MC, Video and other misc functions on an integrated monolithic die. The candidate will technically lead and mentor a team of engineers on Physical Design (place and route ) duties both on block, as well as global top-level activities, which includes: top-level floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis, ECO tasks (timing, functional, noise based ECOs), power delivery etc. Good understanding required of all aspects of physical design taking a design from RTL/ Netlist to GDSII and production. In addition the candidate is expected to have close to expert level of skill in a few core areas.

·         The candidates responsibilities will also include flow and methodology development related to the above tasks or new tasks that arise as technology changes. This involves flow design and implementation via coding in various languages. In addition, very strong communication skills and an ability to work in large groups are essential to being successful.

·         Excellent debugging skills is a must, candidate must be more than a tool executor, and knows how to diagnose and devise workarounds for problems.

·         Requirements

·         Minimum 6 years of ASIC physical design experience.
·         Leadership and Mentoring skills a must.
·         Strong Back ground of ASIC Physical Design : Floor planning , P&R extraction, IR Drop  Analysis, timing and Signal Integrity closure.
·         Hands on experience and detailed knowledge in Cadence or Synopsys or Magma ASIC Physical Design Tools
·         Scripting Language with PERL ,TCL,AWK, shell scripting a very big asset.
·         Familiar with Physical Verification is also desirable.

D.   DFT/ATPG Flow/Methodology Engineer:

The job involves developing flows and methodologies for the creation of high quality manufacturing tests for cutting edge designs using structured Design-for-Test (DFT), Automatic Test Pattern Generation (ATPG) and Logic Built-In Self Test (LBIST) techniques/tools. Candidates must have good software engineering skills and strong knowledge of C/C++ and scripting languages such as Perl. Candidates should also be knowledgeable about DFT techniques such as JTAG TAP, MUX-D/LSSD scan, MBIST, on-chip hardware test compression and at-speed test using on-chip PLL. Familiarity with LBIST and architecture/RTL of Design-for-test techniques is an added advantage.

We look forward to your continuous support and more referrals!!!

Please feel free to mail your queries/clarification to the Team – HR.

Team HR.