Wednesday, February 3, 2010

Opportunities in Embedded and ASIC Domain For experienced@ INFOTECH

Contact Person: Vijay.Mail your resume immediately!
Contact #:
We are looking for Sr.Engineers and Leads for Hitec Vertical. Please go through the detailed job descriptions for the position mentioned below and refer your friends, family, relatives and acquaintances for the below requirements. 
WLAN Engineers-Sr.Engineers/Leads:

  • 3-7 yrs of experience with expertise in WinCE/REX/Nucleus/WinMobile/Linux.
  •  Expertise with SDIO/SPI buses, Experience working with Wi-Fi and networking drivers and TCP/IP in general.
  • Experience various cell phone platforms such as Qcom, TI, Infineon etc.
  • Device Driver Development and Porting of Stacks, Middleware/frameworks.
  • Ability to understand client driver, tools and API libraries and be able to port it to the customer’s platform. 
  • Understanding of Network Layer 3 down to Layer 1, specifically hardware centric expertise with strong knowledge of device driver, kernel mode driver and bus interfaces like SDIO. 
  • Candidates should be able to quickly understand the customer’s platform and requirements. Need to interact with clients in understanding the requirements.

Job Location: Bangalore
Experience: 3 to 7 yrs
Qualification: Diploma/B.Tech/M.Tech/MCA/MSC.
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Semi Engineers-Sr.Engineers/Lead

  • 3-7 yrs of experience with expertise in  WinCE/WinMobile/Linux OS 
  • Experience in Pre and Post silicon Development environment, OS porting and bring up on emulators, simulators and development boards.
  • Hands on Board Support Package (BSP), Hardware Diagnostic Applications development.
  • Good knowledge of System internals of an OS – Linux, Windows
  • Device drivers development expertise – USB, PCI, UART, KB, Touch Screen, Connectivity bus  controllers, Timers and DMA
Audio – Audio controller drivers
Video – Display/Video controller drivers
·         Exposure to Device Driver Development and Porting of Stacks, Middleware/frameworks.
·         OS internals : Kernel , File system
  • Need to interact with clients in understanding the requirements and should be able to architect solutions.
  • Complete understanding of the overall system, interactions among various modules/blocks in the system.
  • Working experience with standard body forums and communities.
  • Should be able to understand the technology landscape, have understanding of current limitations and challenges.

Job Location: Bangalore
Experience: 3 to 7 yrs
Qualification: Diploma/B.Tech/M.Tech/MCA/MSC.
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Physical Design - Sr.Engineers/Leads:

  • 4-7 yrs of exp in Physical Design of which min 2.5+ years of experience in Magma place and route tool (talus is a plus).
  • Able to write Magma Tcl scripts. Very good experience in Clock tree Synthesis involving multiple clocks.
  • Should be able to analyze the reports in different timing modes & come up with solutions. Good knowledge of floorplanning, congestion with more than 20-25 memories.
  • Good Understanding of command scripts like fixcell, fixtime & ability to modify & change it to suit the design requirements.
  • Good understanding of Primetime & ability to implement ECOs in Magma (PTSI is a plus).
  • Must have a good knowledge of STA analysis. Have worked on lower technologies 65nm & below.
  • Very good knowledge of Physical verification (DRC/LVS/Antennas) tool such as Calibre. Good analytical & adaptation skills. 

Job Location: Bangalore/Hyderabad
Experience: 4 to 7 yrs
Qualification: Diploma/B.Tech/M.Tech
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DFT - Sr.Engineers/Leads:

  • 4-8 yrs exp in DFT with Logic Vision tools is mandatory.
  • Basic logic design, Verilog RTL and verification back ground with exposure to STA utilizing industry standard tools.
  • Must possess a strong knowledge of DFT including JTAG, Boundary scan, MBIST, LBIST, scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan for at speed testing.
  • Expertise in industry standard EDA tools for DFT such as DFTAdvisor, fastscan/TestKompress, TetraMax, LogicVision.
  • Experience in Full-Chip DFT implementation of Scan, EDT/Adaptive Scan, JTAG, MBIST, Transition and Path delay ATPG.
  • Experience in Gate Level Simulations, Synthesis, STA and Formal Verification.
  • Understanding of ATE and test engineering. Post-Silicon debug.
  • Programming in Perl, tcl, awk and c/c++    

Job Location: Bangalore/Hyderabad
Experience: 4 to 8 yrs
Qualification: Diploma/B.Tech/M.Tech
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ASIC Design- Sr.Engineers/Leads:

  • 5-9 yrs of exp in ASIC Design with following skill set:
  • Expertise in RTL Coding - Verilog/VHDL and exposure to DFT skill set.
  • Strong scripting skills - PERL/TCL.
  • Should have worked on 65nm or lower node multi-million gate tape outs.
  • Experience in closing timing on DDR2/DDR3/PCIE interfaces and expertise in cross-talk analysis and repair.
  • Expertise in Physical Design with focus on clock trees at block and chip level.
  • Should mentor and guide ASIC design engineers.
  • He/She will be responsible for full chip synthesis, writing constraints interfacing with logic design engrs, implementing low power synthesis techniques, timing and SI closure of blocks and full chip.
  • Working with the Physical Design teams, clock tree synthesis strategy for block level as well as chip level, timing closure on DDR2/DDR3/PCIE etc., interfaces, running multi-corner-multi-mode STA, cleaning up constraints working with logic design and DFT teams.

Job Location: Hyderabad
Experience: 5 to 9 yrs
Qualification: Diploma/B.Tech/M.Tech
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Custom Layout - Sr.Engineers/Leads:

  • 4-7yrs of exp. in Custom Layout Standard Cells, I/O or special analog designs such as RF transceivers, LNA, VGA, PLL, DLL, LDO, Bandgap, VCO, ADC,DAC
  • Strong Layout Design Concepts.
  • Experience in Pcell development, maintaining and modifying PDKs
  • Experience in Layout Design tools such as Virtuoso, Virtuoso-XL.
  • Exposure to digital place & route, expertise in SKILL Programming Language
  • Experience in Physical verification and exposure to Calibre, Hercules and Assura.
  • He/She should be able to act as focal point with customers, work and lead a team of 3-4 custom layout engineers on analog layout, physical verification, maintaining PDKs, evaluating them.
  • The candidates should have a strong expertise in some critical layouts such as PLL, DLL, LNA, VGA, ADC, LDO.

Job Location: Bangalore/Hyderabad
Experience: 4 to 7 yrs
Qualification: Diploma/B.Tech/M.Tech.
 

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