Contact Person: mail cv to :
Contact #:
Note: Do not send any resumes which doesn't matches with requirement.It will get rejected.
******************************************** VEDA IIT is conducting VEDA-CET (Common Entrance Test) at JNTUH for MS Program in VLSI Engineering as well as for recruitment of Engineer Trainees in VLSI Logic Design, VLSI Physical Design, Embedded System Design and Analog & Mixed Signal Design for our consortium companies.
Interested candidates need to pay Rs.300/- by DD towards their application and they can apply at http://www.vedaiit.com.
For further details including Examination date, please go to http://www.vedaiit.com/
